The ongoing miniaturization of features of HDI printed circuit boards, IC substrates and the like requires more advanced manufacturing methods than conventional methods such as formation of circuitry by a print and etch method.
A method for manufacture of fine line circuitry known in the art is the semi-additive process (SAP) which starts from a bare dielectric build-up layer (1) having on at least a portion of the back side a copper area which can be for example a contact area (2), and a second dielectric layer (3) attached to the back side of the dielectric build-up layer (1). Such a substrate is shown in FIG. 1a. At least one opening (4) such as a blind micro via is formed by e.g. laser drilling in the build-up layer (1) which extends through the substrate to the copper area (2) on the back side of the build-up layer (1) (FIG. 1b). The dielectric surface of the build-up layer (1) is subjected to a desmear process in the next step which leads to a roughened top surface (5a) of the build-up layer (1) and a roughened surface (5b) of the dielectric side walls of the at least one opening (4) (FIG. 1c).
Further activation of the roughened top surface (5a) and the roughened side walls (5b) by e.g. depositing a noble metal containing activator is necessary for successive electroless plating of copper. Next, a conductive seed layer (6), generally made of copper, is deposited by electroless plating onto the roughened top surface (5a) of the build-up layer (1) and the roughened side walls (5b) of the at least one opening (4) (FIG. 1d). Such a conductive layer (6) usually has a thickness of 0.8 μm to 1.5 μm which is a) required to provide a sufficient electrical conductivity on the roughened top surface (5a) for successive electroplating of copper and b) to ensure that during electroless plating of copper also a sufficient electrical conductivity is provided to the roughened side walls (5b) of the at least one opening (4).
A thicker layer of copper (8) is then selectively electroplated into openings of a patterned resist layer (7) onto the roughened and activated top surface of the build-up layer (1) and the roughened and activated dielectric walls of the at least one opening (4) (FIG. 1e to f). The patterned resist layer (7) is removed (FIG. 1g) and those portions of the conductive layer (6) which are not covered by electroplated copper (8) are removed by differential etching (FIG. 1h). Such a process is for example disclosed in U.S. Pat. Nos. 6,278,185 B1 and 6,212,769 B1.
One disadvantage of the SAP method is the weak adhesion between the conductive layer (6) and the dielectric surface of the build-up layer (1). The weak adhesion can lead to an undesired delamination of the copper tracks formed by subsequent electroplating of copper onto the conductive layer (6) in later manufacturing steps or later use of the printed circuit board.
Furthermore, the desmear process applied to the top surface of the build-up layer (1) causes a roughening of the dielectric surface. On the one hand, roughening of the dielectric surface is necessary to provide adhesion between the dielectric surface and the conductive layer (6), on the other hand a roughened top surface (5a) of the build-up layer (1) does not allow formation of a fine line circuitry such as one having a line width and inter line spacing of 10 μm or less.
A roughened top surface of the build-up layer (1) requires severe etching conditions in order to remove those portions of the conductive layer (6) from those areas which are not covered by electroplated copper (8). Severe etch conditions lead to an undesired attack of the copper layer (8) and the desired shape of electroplated copper features can not be achieved.
A method for improving the adhesion of a first metal layer on a smooth dielectric surface is disclosed in U.S. 2011/0247865 A1. A polymer adhesive layer which can interact with a plating catalyst or precursor thereof is deposited onto a smooth dielectric layer and thereby the adhesion between the dielectric layer and a first metal layer deposited thereon is increased. Said polymeric adhesion layer is attacked when smear and other undesired residues formed during via formation is removed from the contact pad and the side walls of the via. This cleaning step is mandatory for metallization of the via in later process steps. Accordingly, undesired wedges at the interface polymer adhesion layer/first metal layer/side wall(s) of the via(s) are formed and thereby the adhesion of the first metal layer on the smooth dielectric surface is reduced.